1. Field of the Invention
The present disclosure relates to cointegration of bulk and SOI semiconductor devices at advanced technology nodes and, more particularly, to an integrated circuit product comprising FET semiconductor devices on SOI substrate portions and FET and/or NONFET semiconductor devices on bulk substrate portions of a semiconductor substrate.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. In particular, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than 1 μm, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than any discreet circuit composed of separate independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs) or simply MOS transistors, and passive elements, such as resistors, e.g., diffusion resistors, and capacitors, integrated on a semiconductor substrate with a given surface area. Typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a FET is that of an electronic switching element, controlling a current through a channel region between two junction regions, referred to as source and drain, by a gate electrode which is disposed over the channel region and to which a voltage relative to source and drain is applied. In common FETs, the channel region extends along the plane between the source and drain regions. Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON state” and a non-conducting state or “OFF state” may be achieved. It is important to note that the characteristic voltage level at which the conductivity state changes (usually called the “threshold voltage”) therefore characterizes the switching behavior of the FET and it is an issue to keep variations in the threshold voltage level low for implementing a well-defined switching characteristic. However, with the threshold voltage depending nontrivially on the transistors' properties, e.g., materials, dimensions, etc., the implementation of a desired threshold voltage value during fabrication processes involves careful adjustment and fine-tuning during the fabrication process, which makes the fabrication of advanced semiconductor devices increasingly complex.
The continued miniaturization of semiconductor devices into the deep submicron regime becomes more and more challenging with smaller dimensions. One of the several manufacturing strategies employed herein is the implementation of SOI technologies. SOI (silicon-on-insulator) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitances and short channel effects, thereby improving performance. Semiconductor devices on the basis of SOI differ from conventional semiconductor devices formed on a bulk substrate in that the silicon junction is formed above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon-on-sapphire or SOS devices). The choice of insulator depends largely on the intended application, with sapphire usually being employed in high performance radio frequency applications and radiation-sensitive applications, and silicon dioxide providing for diminished short channel effects in microelectronic devices.
One basically distinguishes between two types of SOI devices, PDSOI (partially depleted SOI) devices and FDSOI (fully depleted SOI) devices. The PDSOI and FDSOI devices differ by the thickness of the semiconductor layer which is disposed over a buried oxide layer, as will be explained with regard to FIG. 1 below. Particularly, the thickness of the semiconductor layer of PDSOI devices is so large that the depletion region formed in the semiconductor layer does not cover the whole channel region provided in the semiconductor layer. Therefore, PDSOI devices behave to a certain extent like bulk semiconductor devices. FDSOI devices, on the other hand, have a semiconductor film formed on the buried oxide layer such that the depletion region in FDSOI devices substantially covers the whole semiconductor film. Due to the increase in the inversion charges in FDSOI devices, these devices have a higher switching speed. Furthermore, FDSOI devices do not require any doping in the channel region. In general, drawbacks of bulk semiconductor devices, like threshold roll-off, higher sub-threshold slop body effect, short channel effects, etc., are reduced.
A conventional SOI-based semiconductor device, as illustrated schematically on the right-hand side of FIG. 1, generally comprises a semiconductor layer 4-1, e.g., on the basis of silicon and/or germanium, being formed on an insulating layer 4-2, e.g., silicon dioxide, which insulating layer 4-2 is often referred to as buried oxide (BOX) layer. The BOX layer 4-2, in turn, is disposed on a semiconductor substrate 4-3, e.g., a silicon substrate. Accordingly, a so-called SOI substrate 4 is formed.
From a physical point of view, the very thin semiconductor film 4-1 over the BOX layer 4-2 enables the semiconductor material under a gate 6 of a transistor, i.e., in the channel region of the semiconductor device, to be fully depleted of charges in case that an appropriate thickness of the semiconductor film 4-1 is chosen. The net effect is that a gate 6 (formed by a gate electrode 6-1 and a gate oxide 6-2) disposed over the SOI substrate 4 can now very tightly control the full volume of the body of a transistor 2 which includes the gate 6. In contrast to the SOI device 2, a bulk device 1 is schematically illustrated on the left-hand side of FIG. 1. Herein, a gate 5 of the bulk device 1, including a gate electrode 5-1 and a gate insulating structure 5-2, is disposed on a semiconductor bulk substrate 3, such as a silicon and/or germanium substrate. In general, due to the tight control of the full volume in the SOI device 2, the SOI device 2 is much better behaved than the bulk device 1, especially because the supply voltage, i.e., the gate voltage, gets lower, and device dimensions are allowed to be scaled without suffering from short channel effects.
The design process flows and design methodologies to design an FDSOI device are the same as those classically used with bulk CMOS techniques, building upon SPICE models suitable for FDSOI devices. Basic advantages of FDSOI devices over bulk devices is the lack of a floating body effect or kink effect associated to PDSOI. Using the SOI technique still leaves the option during the fabrication process to locally remove the top silicon and BOX layers to reach the semiconductor substrate, e.g., the base silicon, and to cointegrate devices on SOI together with (non-geometric critical) bulk devices. However, as indicated in FIG. 1, a cointegration of bulk and SOI devices shows a step height between the SOI substrate 4 and the bulk substrate 3, as it is denoted by the height difference h in FIG. 1. With conventional thicknesses of the top silicon layer 4-1 and the BOX layer 4-2 of about 20 nm, the height difference h substantially is in the range of about 30-50 nm.
On the other hand, it is often desirable to implement different structures on a single wafer, e.g., to integrate more functions into a given wafer surface portion. Therefore, in advanced semiconductor device structures, it may be desirable to form NONFET devices, e.g., capacitors, resistors, diodes, etc., on a bulk substrate in parallel to SOI devices.
In any case, the cointegration of SOI and bulk devices results in removing the top silicon layer and BOX layer over a large area of an SOI substrate, leaving behind a huge topology. As the conventional approach for integrating FDSOI devices is usually employing gate-first techniques, the topology indicated by h in FIG. 1 adds extra complexity and problems to existing integration processes. For example, it turns out to be difficult to form a channel silicon germanium (cSiGe) layer and to provide a sufficiently reliable encapsulation of high-k materials during the fabrication process.
In view of the above-described situation, it is, therefore, desirable to provide methods of forming a semiconductor device structure which overcome the topology issues associated with the cointegration of bulk devices and FDSOI devices and to provide cointegrated bulk and SOI semiconductor devices.